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• W4312095862 abstract "Due to the high parallelism and efficiency, Convolution acceleration and buffer pipeline architecture are common solutions for convolutional neural network (CNN) acceleration, however, existing accelerate solutions exhibit limited performance to accelerate CNN models. This paper presents a novel architecture as YOLO accelerate solution, which based on convolution loop unrolling and data flow pipeline optimization to reduce power consumption and maintain computational accuracy. The convolution loop unrolling algorithm is used to convert the numerous multiplication operations into addition operations to reduce the amount of computation. In the meanwhile, a buffer pipeline method which splits the processing element (PE) array is proposed, further improves the efficiency and optimizes the memory of the accelerator. Moreover, the data of the original model are processed at a low fixed point, reducing the resource consumption of the FPGA. Our proposed architecture can ensure the accuracy of network testing while reducing the power consumption required by the hardware." @default.
• W4312095862 created "2023-01-04" @default.
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• W4312095862 date "2022-11-05" @default.
• W4312095862 modified "2023-09-30" @default.
• W4312095862 title "A power-efficient optimizing framework FPGA accelerator for YOLO" @default.
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• W4312095862 doi "https://doi.org/10.1109/cisp-bmei56279.2022.9980321" @default.
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