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W4312294050 abstract "This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process." @default.
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W4312294050 date "2023-01-01" @default.
W4312294050 modified "2023-10-17" @default.
W4312294050 title "A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ" @default.
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W4312294050 doi "https://doi.org/10.1109/jssc.2022.3222203" @default.
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