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- W4312343323 abstract "This paper describes the research on the development of a SiC Fan-out Wafer level Package for high power application. Electronic Packaging for High Power devices needs to address high temperature capability and a low thermal resistance, as thermal power losses impact the reliability of power devices. These in contrast trend towards higher power densities and performances. A comparison between Fan-out Packages with two different Mold compounds and a SiC Wafer Level Package was performed using FEM Simulation. The simulation shows the high potential of the SiC Fan-out package. It is shown that the thermal resistance of the package is reduced by 72%. This allows to package power devices with much higher power losses compared to mold embedded devices (x3.5). Additionally, we propose a manufacturing process for this package using wafer level back-end processes. It uses deep etching of SiC with an electroplated metal mask, wafer bonding and laser release technologies. It also introduces a SiC nanoparticle filled adhesive to improve thermal conductivity of the bond adhesive. The performed experiments show that up to 37.5wt% SiC nanoparticles could be mixed into the adhesive and spincoated with a good homogeneity on the wafer." @default.
- W4312343323 created "2023-01-04" @default.
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- W4312343323 date "2022-09-13" @default.
- W4312343323 modified "2023-10-03" @default.
- W4312343323 title "Potentials of a SiC Fan-out Wafer Level Package for High Power Application" @default.
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- W4312343323 doi "https://doi.org/10.1109/estc55720.2022.9939379" @default.
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