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- W4312786410 abstract "Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency." @default.
- W4312786410 created "2023-01-05" @default.
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- W4312786410 date "2022-01-01" @default.
- W4312786410 modified "2023-09-27" @default.
- W4312786410 title "Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors" @default.
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- W4312786410 doi "https://doi.org/10.1109/access.2022.3225975" @default.
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