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- W4313019207 abstract "This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128 × 64 (8192) processing units (PUs) with a 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Post-layout simulations of the complete system working on various basic operations in 0.18 μ m CMOS technology are shown." @default.
- W4313019207 created "2023-01-05" @default.
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- W4313019207 date "2022-05-28" @default.
- W4313019207 modified "2023-10-16" @default.
- W4313019207 title "HDC8192: A General Purpose Mixed-Signal CMOS Architecture for Massively Parallel Hyperdimensional Computing" @default.
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- W4313019207 doi "https://doi.org/10.1109/iscas48785.2022.9937910" @default.
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