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• W4313048475 abstract "Spiking-Neural-Networks (SNN) have natural advantages in high-speed signal processing and big data operation. However, due to the complex implementation of synaptic arrays, SNN based accelerators may face low area utilization and high energy consumption. Computing-In-Memory (CIM) shows great potential in performing intensive and high energy efficient computations. In this work, we proposed a JOT-SRAM based Spiking-Neural-Network-In-Memory architecture (SNNIM) with 28nm CMOS technology node. A compact JOT-SRAM bit-cell was developed to realize signed 5bit synapses arrays and configurable bias arrays (SYBIA). The soma array based standard 8T-SRAM (SMTA) stores the soma membrane voltage and the threshold value. A capacitance computation scheme (CCA) between them was proposed to support various SNN operations. The proposed SNNIM achieved energy efficiency of 25.18 TSyOPSI. And the proposed SNNIM achieved 1.79+× better array efficiency compared with previous works." @default.
• W4313048475 created "2023-01-06" @default.
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• W4313048475 date "2022-05-28" @default.
• W4313048475 modified "2023-09-24" @default.
• W4313048475 title "SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation" @default.
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• W4313048475 doi "https://doi.org/10.1109/iscas48785.2022.9937272" @default.
• W4313048475 hasPublicationYear "2022" @default.
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