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- W4313229723 abstract "A multiplicative masked advanced encryption standard (AES)-128/-256 engine with measured side-channel resistance to correlation power and electromagnetic (EM) attacks in Intel 4 CMOS process is presented. While conventional additive masking offers significant improvements in minimum-time-to-disclosure (MTD) for the extracted key bytes, mask compensations in non-linear Sboxes incur >100% area overheads. Multiplicative masking provides a simpler computation of non-linear inverse operation by converting the inputs from an additive to a multiplicative domain. However, multiplicative masked AES designs suffer from zero-value attacks, where “0” valued inputs on Sbox bytes exhibit distinct power signatures compared to a random input byte. The AES engine implements dual-rail zero-value attack detection and mitigation circuits to counteract zero-valued input Sbox bytes. Low-overhead mask conversion and multiplicative Sbox datapath circuits enable <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$1.8times $ </tex-math></inline-formula> and 50% reduction in area and performance overheads, respectively. The countermeasure enables 34000–40 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$000times $ </tex-math></inline-formula> improvements in measured MTD against correlation power and EM attacks compared to an unprotected AES implementation while limiting the area and performance overheads to 65% and 4%, respectively." @default.
- W4313229723 created "2023-01-06" @default.
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- W4313229723 date "2023-04-01" @default.
- W4313229723 modified "2023-10-18" @default.
- W4313229723 title "A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS" @default.
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- W4313229723 doi "https://doi.org/10.1109/jssc.2022.3230372" @default.
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