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- W4313395349 abstract "In 3-D charge trap (CT) NAND flash memory, program/erase (P/E) cycling tests are performed, and the degradation of cell characteristics is investigated. The mechanism of mid-gap voltage (Vmg) shift difference between erased state and programmed state is presented and it is verified by technology computer-aided design (TCAD) simulation configured identically to the real device. TCAD simulation also makes it possible to extract the trap density through the current fitting. Generation of interface traps (Nit) and bulk traps in the tunneling oxide (Not) has the form of a power-law of the number of P/E cycles. Furthermore, it is experimentally found that the degradation of cell characteristics is mainly caused by hole tunneling current from the poly-silicon channel during erase operation." @default.
- W4313395349 created "2023-01-06" @default.
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- W4313395349 date "2022-12-25" @default.
- W4313395349 modified "2023-09-26" @default.
- W4313395349 title "Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide" @default.
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- W4313395349 doi "https://doi.org/10.1587/elex.19.20220465" @default.
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