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- W4313444428 abstract "The era of 5G has taken over the wireless communications to another dimension where there is a necessity for enhanced speeds, low-power consumption, less area intake, and ultra-low latency networks. In this paper, the 5G NR primary synchronization signal block is designed by incorporating high-speed FIR filter which is designed using the systolic array architecture. The high-performance MAC units used in the design are the Vedic multiplier unit and the carry select adder unit. The 5G NR PSS block using proposed systolic FIR filter has been designed using the Xilinx VIVADO 2016.4, and implementation of the synthesized design is carried on ZYNC-7000 series (Zed board). The design for the 5G NR PSS incorporated by proposed systolic FIR filter units has resulted in the total area reduction of 57%. The delay and power improved by 79% and 55%, respectively, due to the proposed high-performance systolic FIR filter incorporated in the design." @default.
- W4313444428 created "2023-01-06" @default.
- W4313444428 creator A5004102896 @default.
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- W4313444428 date "2023-01-01" @default.
- W4313444428 modified "2023-09-25" @default.
- W4313444428 title "Realization of 5G NR Primary Synchronization Signal Detector Using Systolic FIR Filter" @default.
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- W4313444428 doi "https://doi.org/10.1007/978-981-19-5868-7_65" @default.
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