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• W4313477054 abstract "Time interleaving (TI) is an effective approach to higher speed conversion of current-steering digital-to-analog converters (DACs). However, achieving high linearity performance for these TI DACs is challenging during interleaving synchronization, output current summation, and parasitic capacitance control. This article exploits the design of a 6.0-GS/s 14-bit two-channel time-interleaved DAC in a 65-nm CMOS process for communication systems. A novel asymmetric current-tree summation network is proposed to reduce the current summation nonlinearity in the DAC. A differential clock phase and duty-cycle calibration scheme is also adopted while achieving low complexity. Furthermore, a current source layout optimization scheme is proposed that significantly reduces the parasitic capacitance of interleaving switches and improves the linearity. Measurement results of the fabricated DAC show 6–20-dB spurious-free dynamic range (SFDR) improvement with the proposed techniques, achieving >60-dB SFDR up to 1355 MHz and >50-dB SFDR up to the Nyquist." @default.
• W4313477054 created "2023-01-06" @default.
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• W4313477054 date "2023-02-01" @default.
• W4313477054 modified "2023-10-18" @default.
• W4313477054 title "A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration" @default.
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• W4313477054 doi "https://doi.org/10.1109/tvlsi.2022.3232516" @default.
• W4313477054 hasPublicationYear "2023" @default.
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