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• W4313490624 abstract "The development of mobile telecommunications proceeds by increasing the productivity of communication systems, increasing the speed of information transmission, expanding the frequency band, and reducing delays. A software defined radio (SDR) is a programmable transceiver that supports various wireless technologies without the need for hardware upgrades. The best development environment for SDR devices is field-programmable gate arrays (FPGAs) because they provide parallel data processing. The signal in the communication channel is distorted under the influence of many factors: conversion of the signal sampling frequency in the transmitter and receiver, frequency and phase shift of the signal in the communication channel, signal delay, effect of white noise, etc. To reduce the impact of these effects, the receiver includes a synchronization circuit. The receiver contains the following units: automatic gain adjustment; frequency offset correction; recovery of symbol synchronization; restoration of the phase of the carrier frequency; signal demodulation. To ensure fulfillment of the Nyquist criteria and reduction of intersymbol distortions, the transmitter and receiver of the communication system contain a shaping filter with a characteristic of the square root of the raised cosine. Synchronization circles provide a certain range of changes in destabilizing factors. When this range is exceeded, the parameters and quality of the communication system deteriorate. The down-converter of the sampling frequency was studied, and its frequency characteristic was obtained. It is built on the basis of half-band filters according to the quadrature scheme. The frequency shift estimation and correction algorithm is developed according to the maximum likelihood criterion. The symbol synchronization recovery subsystem is based on a phase-locked-frequency circuit (PLL). The main characteristics of the PLL: the time to reach blocking; error detected; transient behavior and traceability; bandwidth. These options depend on the field of application and expected operating conditions. The bandwidth must be sufficient to compensate for deviations between the generator frequency and the reference input signal. The study of the time required by the PLL for synchronization with the reference signal was carried out. The coefficient of bit errors and the magnitude of the error vector for various frequency shifts in the communication channel are determined. The purpose of the article is to evaluate signal distortions in the HDL implementation of the communication system based on the Xilinx Zynq-7000 development environment." @default.
• W4313490624 created "2023-01-06" @default.
• W4313490624 creator A5058041647 @default.
• W4313490624 creator A5084805345 @default.
• W4313490624 date "2022-12-29" @default.
• W4313490624 modified "2023-10-17" @default.
• W4313490624 title "Synchronization of Communication Systems Based on SDR" @default.
• W4313490624 doi "https://doi.org/10.31649/mccs2022.05" @default.
• W4313490624 hasPublicationYear "2022" @default.
• W4313490624 type Work @default.
• W4313490624 citedByCount "0" @default.
• W4313490624 crossrefType "proceedings-article" @default.
• W4313490624 hasAuthorship W4313490624A5058041647 @default.
• W4313490624 hasAuthorship W4313490624A5084805345 @default.
• W4313490624 hasBestOaLocation W43134906241 @default.
• W4313490624 hasConcept C101765175 @default.
• W4313490624 hasConcept C127162648 @default.
• W4313490624 hasConcept C127413603 @default.
• W4313490624 hasConcept C171115542 @default.
• W4313490624 hasConcept C195251586 @default.
• W4313490624 hasConcept C24326235 @default.
• W4313490624 hasConcept C2776257435 @default.
• W4313490624 hasConcept C2778562939 @default.
• W4313490624 hasConcept C40409654 @default.
• W4313490624 hasConcept C41008148 @default.
• W4313490624 hasConcept C44682112 @default.
• W4313490624 hasConcept C47798520 @default.
• W4313490624 hasConcept C49319798 @default.
• W4313490624 hasConcept C51426754 @default.
• W4313490624 hasConcept C76155785 @default.
• W4313490624 hasConcept C76826599 @default.
• W4313490624 hasConceptScore W4313490624C101765175 @default.
• W4313490624 hasConceptScore W4313490624C127162648 @default.
• W4313490624 hasConceptScore W4313490624C127413603 @default.
• W4313490624 hasConceptScore W4313490624C171115542 @default.
• W4313490624 hasConceptScore W4313490624C195251586 @default.
• W4313490624 hasConceptScore W4313490624C24326235 @default.
• W4313490624 hasConceptScore W4313490624C2776257435 @default.
• W4313490624 hasConceptScore W4313490624C2778562939 @default.
• W4313490624 hasConceptScore W4313490624C40409654 @default.
• W4313490624 hasConceptScore W4313490624C41008148 @default.
• W4313490624 hasConceptScore W4313490624C44682112 @default.
• W4313490624 hasConceptScore W4313490624C47798520 @default.
• W4313490624 hasConceptScore W4313490624C49319798 @default.
• W4313490624 hasConceptScore W4313490624C51426754 @default.
• W4313490624 hasConceptScore W4313490624C76155785 @default.
• W4313490624 hasConceptScore W4313490624C76826599 @default.
• W4313490624 hasLocation W43134906241 @default.
• W4313490624 hasOpenAccess W4313490624 @default.
• W4313490624 hasPrimaryLocation W43134906241 @default.
• W4313490624 hasRelatedWork W1981829739 @default.
• W4313490624 hasRelatedWork W2104278593 @default.
• W4313490624 hasRelatedWork W2166717135 @default.
• W4313490624 hasRelatedWork W2247824201 @default.
• W4313490624 hasRelatedWork W2352936579 @default.
• W4313490624 hasRelatedWork W2359317704 @default.
• W4313490624 hasRelatedWork W2374305674 @default.
• W4313490624 hasRelatedWork W2607542579 @default.
• W4313490624 hasRelatedWork W2831289026 @default.
• W4313490624 hasRelatedWork W3021631313 @default.
• W4313490624 isParatext "false" @default.
• W4313490624 isRetracted "false" @default.
• W4313490624 workType "article" @default.