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- W4313490695 abstract "A shift to 3-D NAND technology has resulted in flash memory blocks that include many pages, leading to “big-block” management issues in storage systems. This article experimentally explores endurance variability in 3-D NAND flash memory blocks and finds that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. We find that erase threshold voltage ( <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${V}_{t}{)}$ </tex-math></inline-formula> variation between the layers is the root cause for the observed endurance variation. This variation in endurance among pages can cause severe underutilization of flash memory. To counter these effects and improve the overall utilization of 3-D NAND flash memories, we propose an intrablock wear-leveling algorithm based on dynamic, incremental, and layer-aware downsizing of flash memory blocks." @default.
- W4313490695 created "2023-01-06" @default.
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- W4313490695 date "2023-01-01" @default.
- W4313490695 modified "2023-10-15" @default.
- W4313490695 title "Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3-D NAND Flash Memory" @default.
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- W4313490695 doi "https://doi.org/10.1109/ted.2022.3224420" @default.
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