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- W4313854573 abstract "FPGAs are currently the most suitable hardware accelerator that can be used to implement and accommodate the non-stop growth of machine learning applications. This paper presents an FPGA architecture with added posit multipliers that outweigh the current IEEE-754 multipliers in terms of delay and area. Since Machine learning algorithms involve a lot of expensive mathematical operations, having such powerful multipliers in the proposed FPGA architecture will execute the needed operations with high efficiency which will make this architecture stand out for machine learning applications without compromising other FPGA applications. Experimental results using Verilog to routing (VTR) on machine learning and non-machine learning benchmarks have shown that our architecture achieves better performance compared with other commercially available FPGAs." @default.
- W4313854573 created "2023-01-10" @default.
- W4313854573 creator A5009672736 @default.
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- W4313854573 date "2022-12-04" @default.
- W4313854573 modified "2023-09-23" @default.
- W4313854573 title "Optimized FPGA Architecture for Machine Learning Applications using Posit Multipliers" @default.
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- W4313854573 doi "https://doi.org/10.1109/icm56065.2022.10005431" @default.
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