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- W4316116710 abstract "With the continued growth in field-programmable gate array (FPGA) capacity and their incorporation into new environments such as datacenters, we have witnessed the introduction of a new class of reconfigurable acceleration devices (RADs) that go beyond conventional FPGA architectures. These devices combine a reconfigurable fabric with coarse-grained domain-specialized accelerator blocks all connected via a high-performance packet-switched network-on-chip (NoC) for efficient system-wide communication. However, we lack the tools necessary to efficiently explore the huge design space for RADs, study the complex interactions between their different components and evaluate various combinations of design choices. In this work, we develop RAD-Sim, a cycle-level architecture simulator that allows rapid application-driven exploration of the design space of novel RADs. To showcase the capabilities of RADSim, we map and simulate a state-of-the-art deep learning (DL) inference overlay on a RAD instance incorporating an FPGA fabric and a complex of hard matrix-vector multiplication engines, communicating over a system-wide NoC. Through this example, we show how RAD-Sim can help architects quantify the effect of changing specific architecture parameters on end-to-end application performance." @default.
- W4316116710 created "2023-01-14" @default.
- W4316116710 creator A5030184404 @default.
- W4316116710 creator A5084078152 @default.
- W4316116710 creator A5090801235 @default.
- W4316116710 date "2023-01-11" @default.
- W4316116710 modified "2023-09-30" @default.
- W4316116710 title "RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices" @default.
- W4316116710 doi "https://doi.org/10.48550/arxiv.2301.04767" @default.
- W4316116710 hasPublicationYear "2023" @default.
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