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• W4316252354 abstract "With increasing core counts and multiple levels of cache memories, scaling multi-threaded and task-level parallel workloads is continuously becoming a challenge. A key challenge to scaling the number of communicating tasks (or threads) is the rate at which existing communication mechanisms scale (in terms of latency and bandwidth). Architectures with hardware accelerated queuing operations have the potential to reduce the latency and improve scalability of moving data between processing elements, reducing synchronization penalties, and thereby improving the performance of task-level parallel workloads. While hardware queues reduce synchronization penalties, they cannot fully hide load-to-use latency, i.e., perfect pipelines often are not realized. There is the potential, however, for better overlap. If the inter-processor communication latency is equal to or less than the time spent processing a message at the consumer, any and all latency may be overlapped while the consumer is processing. We exploit this property to speedup parallel applications above and beyond existing hardware queues." @default.
• W4316252354 created "2023-01-15" @default.
• W4316252354 creator A5011742943 @default.
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• W4316252354 creator A5078434282 @default.
• W4316252354 date "2022-08-29" @default.
• W4316252354 modified "2023-09-26" @default.
• W4316252354 title "SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems" @default.
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• W4316252354 doi "https://doi.org/10.1145/3545008.3545044" @default.
• W4316252354 hasPublicationYear "2022" @default.
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