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- W4316659968 abstract "In this paper, a power amplifier with stacked structure is designed, of which feasibility is analyzed in terms of broadband design and high output power design directions. Subsequently, a two-stage cascaded triple-stacked power amplifier circuit and its layout are designed based on 130-nm CMOS process. The simulation results show that the 3-dB bandwidth of this power amplifier is 1.29-8.65 GHz. The output power exceeds 21-dBm in the range of 2-6 GHz, the power added efficiency(PAE) exceeds 19%. Meanwhile, the power amplifier has positive input and output return loss performance, which is less than −7 dB in the range of 2-6 GHz." @default.
- W4316659968 created "2023-01-17" @default.
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- W4316659968 date "2022-10-28" @default.
- W4316659968 modified "2023-09-26" @default.
- W4316659968 title "Broadband Power Amplifier Design in 130nm CMOS" @default.
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- W4316659968 doi "https://doi.org/10.1109/icicm56102.2022.10011257" @default.
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