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- W4317381873 abstract "The rapid demand for higher density and higher data rate Serdes signals in a single high-speed integrated circuit (IC) package is continuously expanding for emerging data-center, networking and storage applications. Hence, this paper discusses cost-effective substrate design solution for high-density 56Gbps PAM4 channels in a single package by enabling back-side trace design strategy. This is critical for low die-package size ratio packages whereby the die edge is close to package edge owing to package form factor constraint. The package transceivers signal layer-to-layer impedance change, and via-to-via coupling are carefully studied using 3D full-wave electromagnetic (EM) tool solver for optimal performance to meet package electrical specifications. By implementing the proposed back-side trace design strategy, it is estimated to potentially save up to 25% substrate cost comparing to the baseline design owing to package layer count reduction and package size increase avoidance." @default.
- W4317381873 created "2023-01-19" @default.
- W4317381873 creator A5005557328 @default.
- W4317381873 creator A5049941454 @default.
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- W4317381873 date "2022-12-07" @default.
- W4317381873 modified "2023-10-18" @default.
- W4317381873 title "High-Density 56Gbps PAM4 Package Design Enablement with Cost and Performance Optimization" @default.
- W4317381873 cites W2517631748 @default.
- W4317381873 cites W3010520654 @default.
- W4317381873 doi "https://doi.org/10.1109/eptc56328.2022.10013263" @default.
- W4317381873 hasPublicationYear "2022" @default.
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