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• W4320170196 endingPage "1648" @default.
• W4320170196 startingPage "1639" @default.
• W4320170196 abstract "With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 °C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications." @default.
• W4320170196 created "2023-02-13" @default.
• W4320170196 creator A5021457401 @default.
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• W4320170196 date "2023-04-01" @default.
• W4320170196 modified "2023-10-18" @default.
• W4320170196 title "A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications" @default.
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• W4320170196 doi "https://doi.org/10.1109/tcsi.2023.3237706" @default.
• W4320170196 hasPublicationYear "2023" @default.
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