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- W4321069664 abstract "This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed." @default.
- W4321069664 created "2023-02-17" @default.
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- W4321069664 date "2018-05-08" @default.
- W4321069664 modified "2023-09-29" @default.
- W4321069664 title "Hierarchical Temporal Memory using Memristor Networks: A Survey" @default.
- W4321069664 doi "https://doi.org/10.48550/arxiv.1805.02921" @default.
- W4321069664 hasPublicationYear "2018" @default.
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