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• W4321608049 abstract "In harsh environments such as space, radiation and charged particles cause Single-Event Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Single-Event Transients</i> (SETs), but incur a minimum of 3 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$times$</tex-math> </inline-formula> cost in area. <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Single-Event Upsets</i> (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Time To Detect</i> (TTD) before repair, during which other events can occur and compromise the system. <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Field Programmable Gate Arrays</i> (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. In this paper, we propose <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>In-Memory Error Code Correction Checking</i> (IMECCC), a method to replace memory scrubbing and improve FPGA configuration memory protection in high radiation environments. Our method allows asynchronous SEU detection, and replaces the scrubbing’s variable time to detect with a fixed TTD. We show that IMECCC reduces FPGA’s TTD by at least 116,000 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$times$</tex-math> </inline-formula> on average, with an area increase of 1.56 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$times$</tex-math> </inline-formula> , using a test architecture resembling a Xilinx Virtex 5 QV at a 60MHz scrubbing frequency." @default.
• W4321608049 created "2023-02-24" @default.
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• W4321608049 date "2023-05-01" @default.
• W4321608049 modified "2023-10-01" @default.
• W4321608049 title "Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking" @default.
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• W4321608049 doi "https://doi.org/10.1109/tcsi.2023.3243644" @default.
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