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- W4323568045 abstract "Abstract In present digital world, the data transmitted over network has become worldwide. The information compiled, processed and communicated in Bits and bytes of digital format over communication channels. For secure communication an advanced encryption Standard (AES) cryptographic algorithm is employed to avoid the risk of secret information tampering. This Research article predominantly focuses on low power and low area hardware architecture designed using Field Programmable Gate array. The novel architecture is derived by employing composite field arithmetic for substitute byte and inverse substitute bytes operation. By this approach the unwanted delay occurs during the Look up table (LUT) method has been averted. Optimized Positive polarity reed Muller (OPPRM) architecture is introduced in order to minimize the hardware utilization, eventually subpipeling technique has brought in, to enhance the speed of the architecture. The Performance metrics of OPPRM-AES is evaluated with respect to Bonded IPADS, Slice, LUTS, Number of slices, Static as well as Dynamic Power. The performance of a proposed architecture is compared with AES-PPRM, AES-CFA and AES-ECG.The architecture is implemented onto Zynq ZC702 Evaluation Board and the simulation is performed through the vivado 2019.1 software." @default.
- W4323568045 created "2023-03-09" @default.
- W4323568045 creator A5040616150 @default.
- W4323568045 creator A5044074621 @default.
- W4323568045 date "2023-03-08" @default.
- W4323568045 modified "2023-10-18" @default.
- W4323568045 title "Low Power FPGA Implementation of an Efficient AES- SBOX Realization for Health Care Applications" @default.
- W4323568045 doi "https://doi.org/10.21203/rs.3.rs-2646986/v1" @default.
- W4323568045 hasPublicationYear "2023" @default.
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