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- W4323767290 abstract "A frequency-tunable phase-locked loop (PLL) applied in high-energy particle detectors has been developed. To achieve high detection efficiency, high requirements are promoted for an on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$LC$ </tex-math></inline-formula> voltage-controlled oscillator ( <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$LC$ </tex-math></inline-formula> -VCO) is used to generate the local clock. A third-order MASH sigma-delta ( <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$Sigma -Delta $ </tex-math></inline-formula> ) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. To further reduce the phase noise (PN), preset and postset binary frequency dividers are employed. In the prototype chip, a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180-nm CMOS process. It costs an area of 1.29 mm2 and a power of 8.1 mW at a 1.8-V power supply. The measured output frequency range is 400–530 MHz with a reference frequency of 25–35 MHz. The rms jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than −61 dBc, and the PN at 1-MHz frequency offset is less than −113 dBc/Hz." @default.
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- W4323767290 date "2023-04-01" @default.
- W4323767290 modified "2023-10-16" @default.
- W4323767290 title "A Frequency-Tunable Fractional-N PLL for High-Energy Physics Experiments" @default.
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- W4323767290 doi "https://doi.org/10.1109/tns.2023.3254645" @default.
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