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- W4328026585 abstract "With the latching input feature on each end of the clock, the dual edge triggered flip-flop (DET-FF) can boost energy performance compared to the single edge triggered flip-flop (SET-FF). For the actual performance at low voltage as a nearby circuit, the proposed bug immune dual edge triggered flip-flop (BI_DET_FF) layout will meet the requirement. This BI_DET_FF reduces power intake, space and will increase the rate and performance of the gadget and may offer completely bug free output. The BI_DET_FF design is modeled and authorized via the SPICE with the range of 0.4–1 V power supply. Delay and power analysis were performed in near threshold and super threshold with technology of 130, 90, 65, 45, 32, 22 and 16 nm. Outcome evaluation and comparisons with existing designs confirmed that the proposed BI-DET-FF can function at a minimum voltage of 0.4 V at temperatures ranging from −60 to 100 °C as long as it holds a very fine power delay product (PDP) and energy efficiency. This design may be used for energy restricted IoT applications." @default.
- W4328026585 created "2023-03-22" @default.
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- W4328026585 date "2023-01-01" @default.
- W4328026585 modified "2023-09-30" @default.
- W4328026585 title "Near Threshold Operation Based a Bug Immune DET-FF for IoT Applications" @default.
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- W4328026585 doi "https://doi.org/10.1007/978-981-19-8825-7_41" @default.
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