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- W4353005497 abstract "This work proposes a two-way transposable SRAM computation-in-memory (CIM) macro for inference and training in convolutional neural networks (CNNs). A novel 9T SRAM bitcell conducts local two-way computing without shared processing units, achieving higher processing throughput from every bit-cell operating in one CIM cycle. This work also proposes a probabilitybased single-slope (SS) and successive approximation (SAR) hybrid analog-to-digital converter (ADC) for energy efficiency improvement by utilizing the probability density function of multiply-and-accumulation (MAC). The proposed ADC also supports the ReLU-based zero skip function without additional circuitry. The prototype was fabricated in 180nm CMOS technology and achieved an energy efficiency of 6.61 (1.65) TOPS/W for inference (training)." @default.
- W4353005497 created "2023-03-23" @default.
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- W4353005497 date "2023-01-01" @default.
- W4353005497 modified "2023-09-23" @default.
- W4353005497 title "Transposable 9T-SRAM Computation-In-Memory for on-Chip Learning With Probability-Based Single-Slope SAR Hybrid ADC for Edge Devices" @default.
- W4353005497 doi "https://doi.org/10.1109/lssc.2023.3260090" @default.
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