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- W4360994081 abstract "Using the Modified Gate Diffusion Input (GDI) approach, a 4-bit Odd Parity Generator/Checker is constructed in this study using CMOS XNOR and CMOS XOR gates. The CMOS XNOR Gate is also realized using Conventional, Complementary Pass Transistor Logic (CPL), Dual Pass Transistor Logic (DPL) & Modified Gate Diffusion Input (GDI) techniques out of which MGDI emerges out to be the most efficient one. The simulation of the above techniques at 180nm VLSI Technology shows that MGDI technique consumes 74.47%,16.21%,33.83% less power than conventional, CPL and DPL techniques respectively. Two new basic gate realization techniques have also been proposed namely CPL-Hybrid (CPLH) and DPL-Hybrid. CPLH technique shows 3.13% less average power dissipation and 16.54% less average propagation delay than MGDI technique in 25KHz to 100MHz frequency range." @default.
- W4360994081 created "2023-03-30" @default.
- W4360994081 creator A5001071368 @default.
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- W4360994081 date "2023-01-06" @default.
- W4360994081 modified "2023-09-24" @default.
- W4360994081 title "Low Power Architecture of 4-bit Odd Parity Generator/Checker Scheme" @default.
- W4360994081 doi "https://doi.org/10.1109/icpces57104.2023.10075976" @default.
- W4360994081 hasPublicationYear "2023" @default.
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