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• W4361767075 abstract "A fully integrated receiver employs a heterodyne architecture with 270- and 27-GHz local oscillators to alleviate phase mismatch issues. The system incorporates three on-chip phase-locked loops (PLLs) to generate the local oscillator phases for both downconversions. Realized in 28-nm CMOS technology, the prototype exhibits a noise figure of 16–20 dB, a gain of 17–21 dB, and a 1-dB compression point of −17.3 dBm. The phase noise (PN) of the 270-GHz PLL is −105 dBc/Hz at 10-MHz offset, amounting to an integrated jitter of 106 fs from 10 kHz to 10 MHz." @default.
• W4361767075 created "2023-04-04" @default.
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• W4361767075 date "2023-08-01" @default.
• W4361767075 modified "2023-09-30" @default.
• W4361767075 title "A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation" @default.
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• W4361767075 doi "https://doi.org/10.1109/jssc.2023.3257820" @default.
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