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- W4364302714 abstract "Usually, the convergence of adaptation algorithm for the coefficients of equalization in high speed SERDES is verified using Mixed signal simulation or in MATLAB™. However, Mixed signal simulation is very time consuming and often not performed on time to catch issues before silicon. Although, MATLAB™ based simulation of adaptation algorithms is faster, but actual RTL and firmware implementations can differ from MATLAB model and often, issues appear on silicon. In this paper, a frequency domain modelling approach for analog components and the channel using System Verilog (SV) is proposed for best suited digital simulation sampling frequency for accuracy and speed of the simulation. This method is demonstrated using D-PHY 3.0 receiver with a Continuous Time Linear Equalizer (CTLE), Early-late edge-based equalization error detection technique which feeds an adaptation algorithm in RTL and a lossy channel. The convergence and effectiveness of the adaptation algorithm for the boost setting of the CTLE is verified using standard digital simulation." @default.
- W4364302714 created "2023-04-12" @default.
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- W4364302714 date "2023-01-01" @default.
- W4364302714 modified "2023-10-16" @default.
- W4364302714 title "SV Based Fast & Accurate Verification Methodology for CTLE Adaptation Algorithm" @default.
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- W4364302714 doi "https://doi.org/10.1109/vlsid57277.2023.00064" @default.
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