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- W4365131127 abstract "In-memory computing (IMC) based on static random access memory (SRAM) is a promising solution to enable highly energy-efficient multiply-accumulate (MAC) operations for machine learning accelerators. In this paper, an in-SRAM computing technique is proposed by using a dual-six-transistor (dual-6T) SRAM cell. The dual-6T SRAM cell is composed of two conventional-6T-SRAM-cell-like 6T cells with split wordlines, achieving a compact array layout. With specialized coding, the dual-6T SRAM circuit is one of the few in-memory accelerators which support parallel MAC operations with both ternary activation and ternary weight. A <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$128times 64$</tex> memory array is implemented in a 55-nm low-power CMOS technology. Due to the compact bitcell topology and smart coding, the proposed dual-6T memory array achieves up to 635 TOPS/W energy efficiency @ 100 MHz and 38.84 TOPS/mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> peak area efficiency @ 350 MHz, which is competitive among the state-of-the-art in-memory computing MAC accelerators." @default.
- W4365131127 created "2023-04-13" @default.
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- W4365131127 date "2022-11-11" @default.
- W4365131127 modified "2023-09-30" @default.
- W4365131127 title "Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks" @default.
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- W4365131127 doi "https://doi.org/10.1109/apccas55924.2022.10090389" @default.
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