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• W4366975703 abstract "With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling. In this work, z-interference mechanisms were investigated in the programming operation with the aid of Technology Computer-Aided Design (TCAD) and silicon data verification. It was found that the inter-cell trapped charges are one of the factors causing z-interference after cell programming, and these trapped charges can be modulated during programming. Thus, a novel program scheme is proposed to suppress the z-interference by reducing the pass voltage (Vpass) of the adjacent cells during programming. As a result, the proposed scheme suppresses the Vth shift of 40.1% for erased cells with Lg/Ls = 31/20 nm. In addition, this work further analyzes the optimization and balance of program disturbance and z-interference with the scaling of cell Lg-Ls based on the proposed scheme." @default.
• W4366975703 created "2023-04-27" @default.
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• W4366975703 date "2023-04-21" @default.
• W4366975703 modified "2023-09-27" @default.
• W4366975703 title "A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory" @default.
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• W4366975703 doi "https://doi.org/10.3390/mi14040896" @default.
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• W4366975703 hasPublicationYear "2023" @default.
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