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- W4367591616 abstract "The variables of a high-level behaviour are mapped to hardware registers during register allocation (RA) in high-level synthesis (HLS). Reverse engineering such mapping is a challenging task due to possible many-to-many relations. In this paper, we propose an satisfiability modulo theory (SMT)-based reverse engineering framework to extract the register to variable mapping in HLS for efficient correlation between input C/C++ and the corresponding RTL generated by the HLS tool. In our method, we first extract a C-like behaviour, called RTL-C from RTL. Both the RTL-C and the input C are next converted to static single assignment (SSA) form. A satisfiability problem is then formulated to obtain the register to variable mapping from C and RTL-C. Finally, the registers in RTL-C are replaced by the corresponding variables in C using the mapping information to obtain the equivalent C code from RTL. The generated C code would be helpful for the algorithm developers to understand the RTL code and to reduce the RTL verification time as well. The proposed method is implemented and tested for several programmes. The experimental results demonstrate the usefulness of the proposed method." @default.
- W4367591616 created "2023-05-02" @default.
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- W4367591616 date "2023-01-01" @default.
- W4367591616 modified "2023-10-16" @default.
- W4367591616 title "An SMT-Based Reverse Engineering of Register Allocation in High-Level Synthesis" @default.
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- W4367591616 doi "https://doi.org/10.1007/978-981-99-0055-8_27" @default.
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