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• W4375798886 abstract "Reconfigurable subsampling mixer-first RF front-end is a potential candidate for low-power applications as it operates at a low clock frequency and hence consumes low power. However, the subsampling down-conversion has not been employed in mixer-first RF front-ends due to the disadvantage of high noise figure from inherent noise folding and lack of RF port impedance matching because of nonzero IF down-conversion. To address the above two issues, first, a subsampling multipath down-conversion mixer scheme is proposed for rejecting <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$3f_{s}/4$ </tex-math></inline-formula> and <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$5f_{s}/4$ </tex-math></inline-formula> down-conversions, thereby alleviating the effect of noise folding, leading to low noise figure. Second, an IF-stage impedance matching scheme is proposed that provides <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$50~Omega $ </tex-math></inline-formula> matching at the RF port of the mixer using an IF-LNA in shunt with an <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$M$ </tex-math></inline-formula> -phase switch-capacitor filter. The analysis of the proposed scheme in terms of noise figure, conversion gain, and harmonic rejection is presented. The proposed subsampling mixer-first RF front-end is implemented in 1.2 V, 65-nm CMOS technology. The prototype occupies an active area of 0.33 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , the switch-capacitor mixer and <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$M$ </tex-math></inline-formula> -phase filter consume <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$400~mu text{W}$ </tex-math></inline-formula> of power, and IF amplifier and nonoverlapping clock generation circuit consume 25 mW and 6–12.6 mW of power, respectively. The RF front-end achieves a 6.5-dB noise figure, 15.1-dB conversion gain, 50-dB harmonic rejection ratio (HRR), and +10-dBm IB-IIP <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> ." @default.
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• W4375798886 date "2023-07-01" @default.
• W4375798886 modified "2023-09-26" @default.
• W4375798886 title "0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS" @default.
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• W4375798886 doi "https://doi.org/10.1109/tvlsi.2023.3269011" @default.
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