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- W4377230425 abstract "The goal of this work is to design a half adder circuit for a multiplier with the considerations of low power dissipation and area reduction under the supply voltage of 1V. The novelty that is presented in this paper is the implementation of Pass Transistor Logic (PTL) technique to enhance the performance of adder logic. In comparison to previous studies, there has been a drastic reduction of transistors in terms of area, delay, and power. The proposed work reduces the power dissipation of the array multiplier. According to simulation results, the suggested design dissipates 1.105 $mu$W of power and 2.09 ns of delay for 10 transistors in half adder logic and 1.094 $mu$W of power and 2.14 ns of delay for 1S transistors in full adder logic. The proposed logic is designed and simulated in a 90 nm CMOS process." @default.
- W4377230425 created "2023-05-23" @default.
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- W4377230425 date "2023-03-23" @default.
- W4377230425 modified "2023-09-30" @default.
- W4377230425 title "Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process" @default.
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- W4377230425 doi "https://doi.org/10.1109/icspc57692.2023.10125717" @default.
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