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- W4377711486 abstract "This article presents an evaluation of the CMOS logic performance of a junctionless (JL) forksheet based on 3-D numerical simulation. The study investigates the transfer characteristics and gate capacitance of the JL-forksheet with channel doping ranging from <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${1} times {10}^{{19}}$ </tex-math></inline-formula> to <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${6} times {10}^{{19}}/text {cm}^{{3}}$ </tex-math></inline-formula> , to determine the optimal performance of the device. Results show that due to its lower gate capacitance, the JL-forksheet has a lower intrinsic delay than the IM-forksheet. Moreover, the JL-forksheet demonstrates improved logic performance in terms of rise time, fall time, propagation delay, and maximum oscillation frequency, with improvements of at least 25%, 35%, 17%, and 21%, respectively, as compared to the IM-forksheet. Based on its simple fabrication process, better power efficiency, and improved digital logic performance at the sub-2 nm technology node (N2), the JL-forksheet exhibits strong potential as a high-performance CMOS logic solution in the post-Moore era." @default.
- W4377711486 created "2023-05-24" @default.
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- W4377711486 date "2023-07-01" @default.
- W4377711486 modified "2023-09-28" @default.
- W4377711486 title "A Simulation Study of Junctionless Forksheet on Sub-2 nm Node Logic Applications" @default.
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- W4377711486 doi "https://doi.org/10.1109/ted.2023.3274621" @default.
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