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- W4378805945 abstract "There has been a long-standing challenge in modeling the effects of transistor aging in static timing analysis (STA). Aging causes threshold voltage shift and mobility degradation which changes timing characteristics of logic gates and poses risk of timing failure of digital circuit. However, due to its strong dependence on signal activity, stress voltage/temperature condition, and operation lifetime, an accurate yet computationally affordable approach in STA is long-overdue. The most common practice in industry employs a derate-based methodology. A large guard band can guarantee the circuit always to be clocked at a sustainable working frequency under different stress condition, however, it also reduces the time-zero circuit performance target and undermines the benefit of technology scaling. In this presentation, we will showcase Synopsys's aging-aware STA technology that is accurate and computationally affordable. Our innovation consists of aged library characterization, ML based mission profile scalable model, path-based aging aware timing analysis, and aging HSPICE circuit simulation." @default.
- W4378805945 created "2023-06-01" @default.
- W4378805945 creator A5009810215 @default.
- W4378805945 date "2023-04-17" @default.
- W4378805945 modified "2023-09-28" @default.
- W4378805945 title "Accurate and Efficient Aging-aware Static Timing Analysis" @default.
- W4378805945 doi "https://doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134260" @default.
- W4378805945 hasPublicationYear "2023" @default.
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