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- W4380048213 abstract "Abstract This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz." @default.
- W4380048213 created "2023-06-10" @default.
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- W4380048213 date "2023-06-01" @default.
- W4380048213 modified "2023-10-12" @default.
- W4380048213 title "A digital delay locked loop with a monotonic delay line" @default.
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- W4380048213 doi "https://doi.org/10.1049/ell2.12837" @default.
- W4380048213 hasPublicationYear "2023" @default.
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