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- W4380994080 abstract "In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256x64 array in 28nm CMOS technology. Post-simulations show successful read operation at 0.25V with 1.11{mu}s read delay, and the minimum energy required is 1.69pJ at 0.4V." @default.
- W4380994080 created "2023-06-17" @default.
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- W4380994080 date "2023-06-15" @default.
- W4380994080 modified "2023-10-17" @default.
- W4380994080 title "Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection" @default.
- W4380994080 doi "https://doi.org/10.48550/arxiv.2306.08936" @default.
- W4380994080 hasPublicationYear "2023" @default.
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