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- W4381747265 abstract "Multiprocessor system-on-chip (MPSoC) architectures with an increasing number of cores benefit from Network-on-Chip (NoC) communication methods, which are robust and scalable. Ultimately, router performance depends on the microarchitecture of the router and its routing algorithms, which determine their throughput and latency properties. During packet travel through the network, routing algorithms are notably crucial NoC router design options. For look-ahead routing, individual first computes the desired output port, which is establishing its local blockage scenario, after it transfers the flits to the neighboring router’s desired output ports. This paper proposes a synchronous predictive routing computing for Distributed Scalable Predictable Interconnect Network (DSPIN) along with RTL implementation and analysis via some popular routing algorithms consecrated toward 2D-Mesh network topographic anatomy. Parametrized Verilog HDL has been used for the RTL implementations, and power, area, and delay (PAD) analysis has been accomplished by Xilinx Vivado. Power dissipation for the design has been estimated with help of Xpower analyzer and Xpower estimator." @default.
- W4381747265 created "2023-06-24" @default.
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- W4381747265 date "2023-01-01" @default.
- W4381747265 modified "2023-10-18" @default.
- W4381747265 title "FPGA Implementations and Performance Analysis of Different Routing Algorithms for the 2D-Mesh Network-On-Chip" @default.
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- W4381747265 doi "https://doi.org/10.1007/978-981-99-1472-2_15" @default.
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