Matches in SemOpenAlex for { <https://semopenalex.org/work/W4382020311> ?p ?o ?g. }
Showing items 1 to 79 of
79
with 100 items per page.
- W4382020311 endingPage "17019" @default.
- W4382020311 startingPage "17000" @default.
- W4382020311 abstract "Abstract RISC-V set architecture is playing an increasingly important role in processor technology due to its open instructions which allow researchers to build and improve computing systems. However, many RISC-V architectures exist in multi-core architecture with complex designs, large area, and high-power consumption. This paper studies an open-source multi-core RISC-V processor in a simple design with less power consumption. The processor depends on an open-source single RISC-V core processor, Taiga. Two cores of Taiga are integrated on a single chip while addressing issues related to cache coherence, interconnect, and memory design. A solution has been developed to achieve data coherence between implemented caches and the main memory; its architecture depends on the snoopy protocol. A hardware-customized peripheral unit has been implemented to achieve the management process among operated cores’ tasks. For more consistent and highly controlled memory storage, the main memory unit has been designed in dual-port based on a specific protocol in the interface, and 8192 lines and word addressable unit. As the UART is common in several devices and processors for communication, the UART as a peripheral customized device has been appended for communication with other devices. The processor has been implemented in System Verilog HDL and extensively tested on various testbenches to ensure correct functionality. Hence, the system performance has been evaluated using the CoreMark benchmark, and achieved 4.605 CoreMark/MHz on Zedboard (FPGA Xilinx family) with a maximum operating frequency 98 MHz. The results indicate that the processor performs comparably to state-of-the-art multi-core processors, while offering a simpler and more power-efficient design. Overall, the research demonstrates the potentialof RISC-V architecture in creating a simple and power-efficient multi-core RISC-V processor." @default.
- W4382020311 created "2023-06-27" @default.
- W4382020311 creator A5040776311 @default.
- W4382020311 creator A5073837381 @default.
- W4382020311 creator A5081947445 @default.
- W4382020311 date "2023-05-05" @default.
- W4382020311 modified "2023-10-17" @default.
- W4382020311 title "Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor" @default.
- W4382020311 cites W2159545333 @default.
- W4382020311 cites W2787006802 @default.
- W4382020311 cites W2794463932 @default.
- W4382020311 cites W2995047564 @default.
- W4382020311 cites W3092543472 @default.
- W4382020311 cites W3114262462 @default.
- W4382020311 cites W3197345780 @default.
- W4382020311 cites W4206312566 @default.
- W4382020311 cites W4285387002 @default.
- W4382020311 cites W4311122829 @default.
- W4382020311 doi "https://doi.org/10.1007/s11227-023-05304-1" @default.
- W4382020311 hasPublicationYear "2023" @default.
- W4382020311 type Work @default.
- W4382020311 citedByCount "0" @default.
- W4382020311 crossrefType "journal-article" @default.
- W4382020311 hasAuthorship W4382020311A5040776311 @default.
- W4382020311 hasAuthorship W4382020311A5073837381 @default.
- W4382020311 hasAuthorship W4382020311A5081947445 @default.
- W4382020311 hasBestOaLocation W43820203111 @default.
- W4382020311 hasConcept C111919701 @default.
- W4382020311 hasConcept C115537543 @default.
- W4382020311 hasConcept C118524514 @default.
- W4382020311 hasConcept C126298526 @default.
- W4382020311 hasConcept C141917322 @default.
- W4382020311 hasConcept C149635348 @default.
- W4382020311 hasConcept C161911788 @default.
- W4382020311 hasConcept C165005293 @default.
- W4382020311 hasConcept C189783530 @default.
- W4382020311 hasConcept C202491316 @default.
- W4382020311 hasConcept C38556500 @default.
- W4382020311 hasConcept C41008148 @default.
- W4382020311 hasConcept C526435321 @default.
- W4382020311 hasConcept C76155785 @default.
- W4382020311 hasConcept C78766204 @default.
- W4382020311 hasConcept C9390403 @default.
- W4382020311 hasConceptScore W4382020311C111919701 @default.
- W4382020311 hasConceptScore W4382020311C115537543 @default.
- W4382020311 hasConceptScore W4382020311C118524514 @default.
- W4382020311 hasConceptScore W4382020311C126298526 @default.
- W4382020311 hasConceptScore W4382020311C141917322 @default.
- W4382020311 hasConceptScore W4382020311C149635348 @default.
- W4382020311 hasConceptScore W4382020311C161911788 @default.
- W4382020311 hasConceptScore W4382020311C165005293 @default.
- W4382020311 hasConceptScore W4382020311C189783530 @default.
- W4382020311 hasConceptScore W4382020311C202491316 @default.
- W4382020311 hasConceptScore W4382020311C38556500 @default.
- W4382020311 hasConceptScore W4382020311C41008148 @default.
- W4382020311 hasConceptScore W4382020311C526435321 @default.
- W4382020311 hasConceptScore W4382020311C76155785 @default.
- W4382020311 hasConceptScore W4382020311C78766204 @default.
- W4382020311 hasConceptScore W4382020311C9390403 @default.
- W4382020311 hasIssue "15" @default.
- W4382020311 hasLocation W43820203111 @default.
- W4382020311 hasOpenAccess W4382020311 @default.
- W4382020311 hasPrimaryLocation W43820203111 @default.
- W4382020311 hasRelatedWork W146324612 @default.
- W4382020311 hasRelatedWork W182515070 @default.
- W4382020311 hasRelatedWork W2136959550 @default.
- W4382020311 hasRelatedWork W2164026451 @default.
- W4382020311 hasRelatedWork W2537885854 @default.
- W4382020311 hasRelatedWork W2993622674 @default.
- W4382020311 hasRelatedWork W4364303238 @default.
- W4382020311 hasRelatedWork W4367172762 @default.
- W4382020311 hasRelatedWork W4382020311 @default.
- W4382020311 hasRelatedWork W4386213660 @default.
- W4382020311 hasVolume "79" @default.
- W4382020311 isParatext "false" @default.
- W4382020311 isRetracted "false" @default.
- W4382020311 workType "article" @default.