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- W4382118001 abstract "The computational requirements in modern workloads like artificial intelligence (AI), machine learning (ML), etc., demand the necessity of hardware acceleration and partial reconfiguration (PR) on a platform like a field programmable gate array (FPGA). In this work, the extendibility and modularity of reduced instruction set computer (RISC)-V® instruction set architecture (ISA) are combined with the dynamic partial reconfigurable features of contemporary FPGAs, to develop new hardware accelerated computing architecture. The architecture executes the extended instruction as a coprocessor implementation, and the necessary coprocessor logic will be loaded into the PR region in real time. The work also explores the idea of having multiple PR regions and caching frequently used coprocessor logic and evaluates its impact on system performance." @default.
- W4382118001 created "2023-06-27" @default.
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- W4382118001 date "2023-01-01" @default.
- W4382118001 modified "2023-10-03" @default.
- W4382118001 title "Design and Development of an FPGA-Based Real-Time Reconfigurable Computing Platform" @default.
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- W4382118001 doi "https://doi.org/10.1007/978-981-99-1699-3_24" @default.
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