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- W4382536761 abstract "In this paper we present a dynamic entropy generator based on the oscillator jitter, which uses a self-biasing technique to minimize process, voltage, and temperature (PVT) variations. The proposed circuit has the advantage of its intrinsic robustness due to self-biasing design, which eliminates the need of additional calibration steps and simplifies the circuit topology, with a negligible impact in area and power consumption. A frequency deviation below 15 % and a maximum jitter difference of 32 % under PVT variations, is obtained, in a 28 nm CMOS technology circuit prototype. For validation of the proposed circuit technique the IC prototype is compared with a standard ring oscillator and with traditional calibration techniques." @default.
- W4382536761 created "2023-06-30" @default.
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- W4382536761 date "2023-06-18" @default.
- W4382536761 modified "2023-09-25" @default.
- W4382536761 title "Design of a 28nm CMOS Self-Biased Ring Oscillator for Intrinsically Robust PVT TRNG" @default.
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- W4382536761 doi "https://doi.org/10.1109/prime58259.2023.10161976" @default.
- W4382536761 hasPublicationYear "2023" @default.
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