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- W4382808073 abstract "In a conventional design setting, pulsed-latch circuits keep the benefits of both latches and flip-flops, including higher performance and lower power consumption. These benefits are maintained even though the design environment is conventional. Electronic circuits depend on supply voltage that is quadratic in nature, and dynamic power also has this relationship (VDD). Scaling the VDD is the most effective strategy for achieving the goal of reducing the amount of power that is consumed. In recent times, a variety of new approaches to lowering the dynamic power consumption of system-on-chips have been developed. The ability to operate quickly, use little power, set up, and keep their position quickly are all desired qualities in a latch. As a result, this work has attempted to evaluate the performance of various topologies based on criteria such as power, delay, and the number of transistors. In this paper, we explore several different pulse latches that are suitable for low VDD operation." @default.
- W4382808073 created "2023-07-02" @default.
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- W4382808073 date "2023-01-01" @default.
- W4382808073 modified "2023-09-25" @default.
- W4382808073 title "Performance Analysis of Pulsed Latches for Low-Voltage Operation" @default.
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- W4382808073 doi "https://doi.org/10.1007/978-981-99-0973-5_42" @default.
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