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- W4382809582 abstract "Nowadays in semiconductor industries, the design rule checking (DRC) in the VLSI physical design flow is becoming more challenging. The number of DRC errors are increasing day by day with increase in complexity of the circuits. Yield reduces because of DRC violations, so making profitable integrated circuits is a difficult problem for the industry at cutting-edge technological nodes. Many industries and researchers have come up with different ideas to solve this issue and make the DRC faster and more accurate. There is an ardent need for an instantaneous DRC method that could be utilized during layout would be really useful. This paper establishes the proof of concept for a method which uses CNN model for efficient identification of DRC violations for a selected VLSI circuit D-flip flop. The dataset is prepared with the help of the microwind tool. Comparative analysis of the proposed CNN model is done with standard CNN architectures like AlexNet and VGG16 which is presented. The proposed approach is capable of detecting DRC errors with an accuracy of 98.33%. This paper is focused only on errors related to metal, polysilicon, and N-well, and it can also be expanded to other types of DRC errors related to VLSI circuits." @default.
- W4382809582 created "2023-07-02" @default.
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- W4382809582 date "2023-01-01" @default.
- W4382809582 modified "2023-10-16" @default.
- W4382809582 title "Automated Design Rule Checker for VLSI Circuits Using Machine Learning" @default.
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- W4382809582 doi "https://doi.org/10.1007/978-981-99-0973-5_36" @default.
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