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- W4383334203 abstract "The purpose of this paper is to theoretically investigate the resistance of backside metallization stacks. The latter serves as a conventional die-attach layer providing an excellent ohmic contact and heat dissipation interface to integrate circuits in semiconductor packaging. Since a typical backside metallization is a stack of different metal layers, one major practical challenge is the estimation of its vertical electrical resistance when it is deposited on a silicon wafer. Here, a simple and fast computation model based on finite elements Ansys software is proposed to calculate the resistance of backside metallization stack by solving the electrostatic equation. A comparative investigation is performed to assess the resistance of the backside metallization stack on both non-structured (ultraflat with average roughness Ra = 0 nm) and structured (average roughness Ra = 200 nm) silicon substrates. To account for the surface roughness of the Si wafer, backside metallization stacks having different thickness ratio have been studied. The variation of the resistance is computed as function of different material thicknesses ratio and for different values of Si electrical conductivities. Finally, the simulation model and the calculated resistance values are assessed through the comparison with experimental data obtained by measuring the total resistance backside metallization stacks via four-points method." @default.
- W4383334203 created "2023-07-07" @default.
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- W4383334203 date "2023-05-10" @default.
- W4383334203 modified "2023-10-18" @default.
- W4383334203 title "Calculation of the resistance of silver-based backside metallization stack for die-attach packaging applications" @default.
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- W4383334203 doi "https://doi.org/10.1109/isse57496.2023.10168500" @default.
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