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• W4383340423 abstract "This article presents a multistack switched-capacitor point-of-load (MSC-PoL) voltage regulation module (VRM) with coupled magnetics for ultrahigh-current chiplet systems. In the MSC-PoL architecture, the stacked switched-capacitor cells split the high input voltage into several intermediate voltage rails, which are loaded with the switched-inductor cells to achieve soft charging and voltage regulation. Automatic capacitor voltage balancing and inductor current sharing are realized during the soft charging process. Many inductors of the switched-inductor cells are coupled into one and operated in interleaving to reduce the inductor current ripple and boost the transient speed. A 48-to-1-V/450-A VRM containing two MSC-PoL modules is built and tested, leveraging high-voltage GaN devices for the front end and high-current silicon devices for the back end. Two ladder-structured coupled inductor designs are developed and compared, one of which installs a leakage magnetic plate to adjust the leakage inductance for lower current ripple. Featuring 3-D stacked packaging, the entire power stage, gate drivers, and bootstrap circuits of one MSC-PoL module are enclosed into a <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$frac{1}{16}$</tex-math></inline-formula> -brick/0.31-in <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$^{3}$</tex-math></inline-formula> /6-mm-thick package. The peak efficiency, the full-load efficiency, and the full-load power density (including both gate loss and size) of the MSC-PoL prototype with and without using the leakage plate are 91.7% and 89.5%, 85.8% and 85.6%, and 621 and 724 W/in <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$^{3}$</tex-math></inline-formula> , respectively. The 6-mm-thick MSC-PoL converter can be embedded into the chiplet or CPU socket, enabling power supply in package for extreme efficiency, density, and control bandwidth." @default.
• W4383340423 created "2023-07-07" @default.
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• W4383340423 date "2023-10-01" @default.
• W4383340423 modified "2023-10-17" @default.
• W4383340423 title "MSC-PoL: Hybrid GaN–Si Multistacked Switched-Capacitor 48-V PwrSiP VRM for Chiplets" @default.
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• W4383340423 doi "https://doi.org/10.1109/tpel.2023.3293022" @default.
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