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- W4383501616 abstract "Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which can effectively improve the computing efficiency of the convolutional neural network (CNN). To improve throughput and computational energy efficiency while maintaining accuracy, this paper proposes an SRAM CIM accelerator with the capacitor-coupling method. Charge-domain based accumulation scheme can reduce the impact of multiplication and accumulation (MAC) unit variations, which makes it possible to increase computational throughput and energy efficiency in a fully-parallel manner. Furthermore, the array size and the mapping of weights are designed to improve the utilization by considering the network characteristics and data volume. At the data flow level, this paper proposes a novel data reuse scheme to make full use of the input data. Besides, design-specific custom instructions based on RISC-V are designed to improve data transfer efficiency. Simulation results show that the proposed SRAM-based accelerator can achieve energy efficiency of 284.7, 71.2, and 17.8 TOPS/W at 2-bit, 4-bit, and 8-bit modes in 28-nm CMOS." @default.
- W4383501616 created "2023-07-08" @default.
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- W4383501616 date "2023-06-11" @default.
- W4383501616 modified "2023-09-27" @default.
- W4383501616 title "RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate" @default.
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- W4383501616 doi "https://doi.org/10.1109/aicas57966.2023.10168630" @default.
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