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- W4384080249 abstract "In this letter, we characterize the commercial 110nm bulk silicon MOSFETs down to 6 K, with a focus on cryogenic capacitorless memory applications. The substrate-induced steep subthreshold swing (SS) and hysteretic loop are observed at low temperatures. At 6K with <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>V</i> <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>D</sub> = 1.8 V, the minimum SS is <0.3 mV/dec and the hysteretic loop is >0.2 V wide with a ~10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>8</sup> ratio of high to low drain current states. For the first time, we demonstrate the cryogenic capacitorless memory operation of bulk silicon MOSFETs. It shows a ~12 μA sense margin, long retention time (on the scale of minutes when T ≤30 K), and high write and read endurance. These features make it promising as a compact capacitorless single-transistor memory for low-temperature applications." @default.
- W4384080249 created "2023-07-13" @default.
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- W4384080249 date "2023-09-01" @default.
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- W4384080249 title "Cryogenic Hysteresis in 110 nm Bulk Silicon MOSFETs for Capacitorless Memory Applications" @default.
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- W4384080249 doi "https://doi.org/10.1109/led.2023.3294638" @default.
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