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- W4384207829 abstract "The requirement of reduced production costs in the domain of integrated circuit(IC) manufacturing and constrained time-to-market are met at the cost of a plethora of security concerns in chip design. In the fourth industrial revolution, where system-on-chip forms the backbone of various electronics, malicious hardware modules known as hardware Trojans within the third-party intellectual property impose a significant security threat. The flexibility and ease of intrusion provided in the earlier stages of design, known as the pre-silicon stage, make it vulnerable to these hardware attacks. Such a scenario further emphasizes the need for effective pre-silicon detection schemes. Since this stage is more vulnerable to hardware attacks. Most existing pre-silicon schemes rely on domain knowledge for feature extraction to develop knowledge-driven but exhibit limited Trojan space exploration. Hence, a proposal that comprises four major stages, viz., multifaceted heterogeneous feature extraction, dynamic hybrid sampling, mutual information-based feature selection, and genetic algorithm-based optimization, has been attempted to handle the challenges. Experimentation on TRIT-TC benchmark circuits resulted in a better predictive value for the chosen test circuits, which proves that the proposal outperforms existing schemes." @default.
- W4384207829 created "2023-07-14" @default.
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- W4384207829 date "2023-10-01" @default.
- W4384207829 modified "2023-10-16" @default.
- W4384207829 title "Graph based heterogeneous feature extraction for enhanced hardware Trojan detection at gate-level using optimized XGBoost algorithm" @default.
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- W4384207829 doi "https://doi.org/10.1016/j.measurement.2023.113320" @default.
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