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• W4384304087 abstract "This paper presents a CMOS image sensor (CIS) integrated with a binarized neural network (BNN) for face detection in always-on image classification applications. We propose a process variation-immune comparator-based row buffer generating edge images that are inputs of the BNN processor. To reduce the power consumption of column-parallel row buffers, we adopted comparator-based switched capacitor (CBSC) circuits. With a proposed auto-zeroed current source block circuit that operates with low supply voltages, we observed a low variation of row buffers’ outputs. The measurement results showed that the σ/μ of the row buffers’ output is decreased by 4% while reducing 28% of power consumption compared to conventional CBSC-based row buffers. The proposed CIS with an in-column BNN processor having a single channel and two hidden layers was fabricated in a 1-poly 4-metal 110nm CIS process. As a measurement result, we achieved an image classification accuracy is 97.75%. Furthermore, the image resolution is 120×120, and the total power consumption of the proposed CIS is 3.78 mW with supply voltages of 2.8 V and 1.5 V at 240 frames per second." @default.
• W4384304087 created "2023-07-15" @default.
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• W4384304087 date "2023-10-01" @default.
• W4384304087 modified "2023-10-15" @default.
• W4384304087 title "A 240 FPS In-column Binarized Neural Network Processing in CMOS Image Sensors" @default.
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• W4384304087 doi "https://doi.org/10.1109/tcsii.2023.3295391" @default.
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