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- W4384484739 abstract "With the development of integrated circuits in recent years, the role of interconnec¬t¬i¬o¬ns between wires in them cannot be ignored, because it leads to functional errors of the circuit. A method has been developed that allows to take into account the effects of interconnections during the clock tree synthesis. The interconnection phenomena in memory testing systems are examined and reduced by enhancing the testing system's clock tree." @default.
- W4384484739 created "2023-07-17" @default.
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- W4384484739 date "2023-01-01" @default.
- W4384484739 modified "2023-10-10" @default.
- W4384484739 title "REDUCING THE CONSEQUENCES OF THE WIRE INTERCONNECTIONS IN INTEGRATED CIRCUITS BY OPTIMIZING THE CLOCK TREE" @default.
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- W4384484739 doi "https://doi.org/10.53297/0002306x-2023.v76.1-93" @default.
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