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• W4384835092 abstract "With the wide deployment of Internet of Things (IoT) solutions, along with the increased demand for incorporating intelligence at the edge, the development of high-performance System-on-Chips (SoC), specifically for edge devices, has gained momentum. Currently, most of the processors used for the development of IoT edge device are ARM architecture based, where license fees are involved. An open-source RISC-V based SoC for IoT edge is the requirement of the day that will accelerate IoT development and widespread deployment. This open-source RISC-V based device needs to be secure and protected from privacy breaches. The first and most crucial step towards developing such a secure and privacy enhanced ethical SoC for the edge, is the choice of RISC-V core. In this paper, the analysis performed for the design choice of the RISC V processor core has been detailed. After surveying the literature, three cores have been shortlisted and synthesized using FPGA device of Virtex® UltraScale+ family from Xilinx. The inferences from the synthesis results and its impact on the architecture of the proposed IoT edge SoC have been presented. The challenges in the design of an ethical edge-IoT SoC have been described. The approach for implementation and evaluation has been discussed." @default.
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• W4384835092 date "2023-05-01" @default.
• W4384835092 modified "2023-10-16" @default.
• W4384835092 title "RISC-V Core for Ethical Intelligent IoT Edge: Analysis & Design Choice" @default.
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• W4384835092 doi "https://doi.org/10.1109/ccgridw59191.2023.00031" @default.
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